1. Field of the Invention
The present invention relates to a semiconductor memory, and in particular to a semiconductor memory which includes an internal test circuit for use in rapidly testing an array of memory cells of the semiconductor memory.
2. Description of the Related Art
With advances which have been made in recent years in semiconductor memory manufacturing technology, there has been a substantial increase in the number of elements which can be formed within a single chip of an integrated circuit. In the case of a dynamic random-access memory (hereinafter referred to as a DRAM), the storage capacity of one chip can now be as high as 16 to 64 megabits, while in the case of a static random access memory (hereinafter referred to as a SRAM), the storage capacity of one chip can be of the order of 4 to 16 megabits. With further advances that can be expected in future semiconductor device technology, greater increases can be anticipated in the amount of storage capacity achievable on one chip. One extremely effective approach to increasing the storage capacity per chip, in the case of a DRAM or SRAM, is to minimize the number of circuit elements, as far as possible. However in the case of a very large-capacity semiconductor memory, due to limitations of package size, number of IC pins, amount of power consumption, etc., it has also been found necessary to minimize the bit width (i.e. the number of bits which are conveyed in parallel) of the data I/O interface between the memory and the exterior. In the case of a 16 megabit semiconductor memory for example, typical values used at present for the I/O data bit width are 1 bit, 4 bits, or 8 bits. Use of such a small value of I/O data bit width has the disadvantage that a very long time is required to test all of the memory cells. In the case of a 16 megabit semiconductor memory having a 1-bit I/O data bit width, for example, only one bit can be written into or read out from the memory cells at each memory access operation. Thus to read or write data to or from all of the memory cells, it is necessary to perform a total of at least 16 million accesses. Considering the case in which the "0" state and the "1" state have each to be written into and read out of every memory cell of a 16 megabit semiconductor memory in order to test all of the cells, it becomes necessary to execute a total of (4.times.16,000,000) accesses. Thus the time required for memory testing becomes excessively long.
In the prior art, as attempts to reduce that problem of excessively long test time, methods have been proposed such as making the bit width of the internal data bus of the memory chip greater than the external I/O data bit width. In that way, by supplying test data from the exterior and then expanding the test data to the larger bit width of the internal bus, the number of memory cells which can be written or read by a single memory access operation can be increased. Moreover it becomes possible to execute internal comparison operations to determine whether data which are written into memory cells are identical to data that are subsequently read out from the cells, with only the comparison results being sent out from the memory to the exterior. The time required for memory testing can thereby be further reduced.
In general, a video memory (referred to hereinafter as a VRAM) is a dual-port memory which is made up of a random access memory (referred to hereinafter as a RAM) with a corresponding random access I/O port, and a serial access memory (referred to hereinafter as a SAM) together with a corresponding serial access I/O port. At present, storage capacity values of 1 to 4 megabits can be achieved for the RAM section of a 1-chip VRAM. The above problem of a long time being required for memory testing also arises with the RAM section of a VRAM. In the prior art, testing of the RAM section of a VRAM has been executed in the same way as for testing a DRAM or SRAM, by utilizing the random access port to the RAM section of the memory, to input test data and to output the test results.
FIG. 1A illustrates a memory cell array in an example of a prior art DRAM, which employs the folded bit line technique, whereby each bit is read out from a pair of memory cells as a differential signal appearing on a pair of bit lines, in order to achieve a high speed of operation. FIG. 1B is a circuit diagram of a portion of the circuit of FIG. 1A, for describing differential data read and write operations. In FIG. 1A, numeral 1 denotes the memory cell array, in which respective memory cells are designated as MC. Respective word line data rows are stored in corresponding rows of the memory cells MC, and an arbitrary one of these word line data rows can be selected during a read or write access operation by applying a selection signal to a corresponding one of the word lines (WL0, WL1, . . . WLn). In practice, the word line selection is determined (by means which are well known in the art and are omitted from the drawings for simplicity) by bits of an address which is supplied to the memory at the time of the read or write access. A selected word line data row is read out as a set of differential signals (i.e. appearing between the bit line pair BL0/BL0, the pair BL1/BL1, and so on) which are transferred via the pairs of bit lines to respective ones of a set of differential sense amplifiers 2, to be amplified thereby. With the folded bit line technique, the successive rows of memory cells are alternately designated as normal phase rows and inverse phase rows. This signifies that in each of the memory cells of a normal phase row (i.e. the rows which are selected by the word lines WL0, WL2, . . . WLn), a "1" state bit is represented by a high (e.g. positive) potential, referred to in the following as the "high" level, while a "0" state bit is represented by a low (e.g. zero) potential, referred to in the following as the "low" level. However in each of the memory cells of an inverse phase row, a "1" state bit is represented by the "low" level while each "0" state bit is represented by the "high" level. The even-numbered word lines (WL0, WL2, . . . ) will therefore be referred to as the normal phase word lines, and the odd-numbered word lines (WL1, WL3, . . . ) as the inverse phase word lines, and the bit lines connected to the normal phase memory cells and to the inverse phase memory cells will similarly be referred to as the normal phase bit lines and inverse phase bit lines.
When a word line data row is selected by addressing the corresponding word line, then resultant amplified differential signals representing the data are produced from the set of differential sense amplifiers 2. A set of these differential signals, representing a number of bits which is equal to the data bit width of the internal data bus 4, is selected from all of the differential signals, by the column selectors 3, and transferred to the internal data bus 4. That is to say, each bit that is read out from or written into the memory cell array 1 from or to the exterior of the memory is transferred as a differential signal via a pair of lines of the internal data bus 4. The read operation will be described referring to FIG. 1B, in which two of the array of memory cells 1, positioned at the intersections of the word lines WL0, WL1 and the bit lines Bl0, BL0 are designated as MC.sub.a and MC.sub.b respectively, the corresponding column selection transistors as 3a, 3b respectively, and the corresponding data lines of the internal data bus 4 as 4a, 4b . Normally the bit lines BL0, BL0 are held at a potential which is midway between the "high" and "low" levels. As a result, if a "1" state bit is stored in MC.sub.a and the word line WL0 is addressed to thereby read out the contents of memory cell MC.sub.a, a "high" level output will be supplied via the column selector 3ato the data line 4aand a "low" level output to the column selector 3b to the data line 4b, from the sense amplifier 2a. A "high" level output, representing a "1" state bit will thereby be produced from the read amplifier, to be transferred to the external I/O data interface of the chip. If on the other hand a "1" state bit is stored in the memory cell MC.sub.b, and the word line WL1 is addressed, then the "low" state contents of MC.sub.b will appear on the bit line BL0, so that again the sense amplifier 2awill supply a "high" level output to the data line 4aand a "low" level output to the data line 4b.
In a similar way, if "0" state data are stored in each of the memory cells MC.sub.a, MC.sub.b, the data lines 4a, 4b will be set to the "low" and "high" levels respectively when either of these memory cells is read out.
It can thus be understood that with such a folded bit line configuration, the number of conductors constituting the internal data bus 4 will be twice the data bit width of the internal data bus, since each bit must be transferred by a pair of data lines of that bus.
The above description has been given assuming that the semiconductor memory is a DRAM, however a similar internal configuration, using such a folded bit line technique with data transferred as differential signal values, is commonly used for a SRAM also.
As described hereinabove, the data bit width of the internal data bus 4 may be made larger than that of the external I/O interface.
FIG. 2 illustrates, in general form, the internal configuration of a prior art type of video random access memory (referred to in the following as a VRAM). The VRAM 100 is formed of a RAM (random access memory) 101 and a SAM (serial ,access memory) 102, together with a random data I/O port 103 and address input port 107 for the RAM 101, and a serial data I/O port 105 and serial clock input terminal 106 for the SAM 102. Control signals for controlling the operation of the VRAM 100 are supplied from an input terminal 104. An arbitrary row of data (e.g. the data for one scan line of a video signal frame) stored in a row of memory cells of the RAM 101 can be transferred in parallel from bit line outputs of the RAM 101 to the SAM 102, to be then outputted serially from the serial data I/O port 105 in synchronism with the serial clock signal. Data can also be transferred serially in via the serial port 105 to the SAM 102 in synchronism with the serial clock signal, whereby an arbitrary row of data can be written in parallel into the RAM 101 from the SAM 102. The internal configuration of the RAM 101 is generally as shown in FIG. 1A and described hereinabove. Respective bit lines of the RAM 101 are coupled (via sense amplifiers) to corresponding parallel inputs of the the SAM 102, i.e. data rows which are transferred in parallel between the RAM 101 and the SAM 102 correspond to the word line data rows of the DRAM of FIG. 1A described above. In the prior art, during testing of the RAM 101, in the same way as described for the memory of FIG. 1A, read and write data are transferred via the random data I/O port 103. To maximize the speed of memory testing by prior art methods, the data bit width of an internal data bus in the RAM 101 which communicates with the random data I/O port is made greater than that of the external I/O data bit width, as described hereinabove. That is to say, during each memory access operation in memory testing by a prior art method, the data bit width of that internal data bus is utilized for reading/writing from/to the memory cells.
With such prior art types of semiconductor memory, in which the data bit width of the internal data bus is increased in order to increase the number of bits which can be simultaneously written into or read out from the memory cells in each memory access, to thereby reduce the time required for memory testing, the bit width of the internal data bus would typically be made 16 bits, for example. Thus the internal data bus would have a total of 32 conductors. Hence, if the bit width of the internal data bus is made large, the area of the chip surface that is occupied by the internal data bus will become excessively large, so that the overall chip size will tend to be increased. An increase in chip size will result in problems of increased levels of connecting lead resistance and capacitance, which will cause a lowering of performance.
Thus it is difficult to achieve a sufficient reduction of the amount of time required for testing a semiconductor memory having a very large degree of storage capacity, simply by increasing the data bit width of the internal data bus of the memory. This problem will become more severe in the case of new types of semiconductor memory which can be expected to be developed in the future, having even greater values of storage capacitance than those which are currently available.